1. Field of the Invention
The present invention relates to integrated circuit technology and to integrated circuits for use in ethernet technology. More particularly, the present invention relates to ethernet transceiver and communications controller integrated circuits and protocols for enabling performance of full duplex ethernet communications in ethernet networks employing separate transmit and receive ports for each node, such as 10Base-T networks. The circuits are downward compatible for use in ethernet networks employing half-duplex ethernet transceivers.
2. The Prior Art
Ethernet CSMA/CD based networks have attained wide spread acceptance and use since their introduction in early 1970's. Currently, ethernet is a half-duplex protocol and most present ethernet implementations use coaxial cable based networks. In the typical coaxial-cable based ethernet configuration, the network is set up in a bus topology, and comprises a plurality of ethernet nodes, each including a transceiver connected to the common bus. Each ethernet transceiver used is a current switch for data transmission on the bus, which is a coaxial cable. Those of ordinary skill in the art will recognize that, due to the existence of only a single communications channel, only one transceiver at a time can transmit data without creating a "collision" on the single bus. All other nodes on the network "listen" to the bus while any one node is transmitting. While transmitting, a node cannot receive data from any other node on the network, although it may receive its own data in a self-receive/loop-back function.
In late 1990, a new ethernet media standard referred to as "10Base-T" was proposed and accepted. Ethernet architectures according to the 10Base-T ethernet standard comprise a star topology, wherein a plurality of remote nodes radiate from a central hub or multiport bridge. Each remote node includes a transceiver which communicates with a corresponding transceiver in the hub. Unlike the single communications channel coaxial-cable based architectures, each remote node in the 10Base-T ethernet architecture employs two pairs of unshielded twisted-pair telephony grade cable as the transmission medium, one pair for transmitting and one pair for receiving. A transceiver is provided in the central hub for each node, as well as circuitry which switches all signals transmitted from one remote node to the other remote node for which it is intended.
Unlike the coaxial cable ethernet configuration scheme wherein collisions which are simultaneous transmission attempts by more than one node are detected by monitoring average DC voltage levels, a collision signal is generated by a transceiver in the 10Base-T configuration if it senses simultaneous data activity on both its transmit and receive pairs. In addition, the loop-back function is implemented in a pseudo fashion in 10Base-T. The result in both coaxial and twisted pair media based ethernet networks is that any node effectively has only a half-duplex media communication channel.
As a part of the ethernet standard ANSI/IEEE Std. 802.3i-1990, and ANSI/IEEE 802.3 CSMA/CD (1990), both expressly incorporated herein by reference, all 10Base-T ethernet networks use Link Integrity Test pulses to protect the network from link segment failures. According to the current protocol, each ethernet transceiver sends a series of link pulses over its transmit twisted pair to the receive twisted pair of the transceiver to which it is connected. The central hub/concentrator typically provides the cross-wiring function needed to implement this architecture. After each pulse is sent, the receiver expects to receive another pulse within a time window beginning 2-7 msec after the initial pulse and ending 25-150 msec after the initial pulse. If the second pulse is received within the acceptable time window, the ethernet link is considered valid. If no pulse is received within this allowable window, the link is considered to be down. When a pulse is again received, the receiver waits for anywhere from 2-10 pulses within a 2-25 msec window to determine that the link is re-established. If a second pulse is received in a time window from 0-2 msec after the initial pulse, the initial pulse is rejected and the timing starts again from the second pulse.
Because of the existence of separate receive and transmit paths to each remote node in 10Base-T ethernet networks, operation in full duplex mode (i.e., simultaneous receive and transmit) is theoretically possible. An ethernet node capable of full duplex communications would preferably be downward compatible with currently available half-duplex 10Base-T systems so that it would be compatible therewith. A method for determining whether the transceiver to which it is connected also has full duplex communications capability is therefore needed. Currently, Intel Corporation of Santa Clara, Calif. markets a pseudo-full-duplex ethernet data-link controller. This controller, designated 82596, cannot transmit a new frame if the receiver is active, and is thus not a true full-duplex transceiver.
Accordingly, it is an object of the present invention to provide a full-duplex 10Base-T ethernet architecture, preferably in the form of a single integrated circuit, which allows any node in a 10Base-T network to determine whether the other ethernet transceiver with which it communicates has full-duplex communication capability and, if so, modify its behavior in conjunction with the data-link controller to establish independent transmit and receive communication channels.